The present invention relates to data generation, and more specifically, to a data generator that can generate fast data having an arbitrary word length.
A signal generator is an apparatus that can store digital waveform data in the storage device such as a memory, hard disk drive (HDD), etc. The digital waveform data may be previously stored data defined by a standard, such as PCI Express or the like, or may be user defined digital waveform data. The digital waveform data is converted by the signal generator into an analog signal output.
One application for a signal generator is in developing a new electronic apparatus. The signal generator may provide an expected output signal from an uncompleted circuit block of the apparatus to a circuit block following the uncompleted circuit block to confirm whether the following circuit block works as expected. Another application is compliance testing where the signal generator provides a signal including intentional jitter or distortions to a circuit under test. Further, the signal generator may be used for measuring characteristics of a fast serial interface such as PCI Express, etc. The signal generator provides a signal having waveform patterns suitable for the characteristic testing and an oscilloscope is used to receive an output from the transmission lines to measure the characteristics with eye pattern display, etc. AWG7000B series signal generators, manufactured and sold by Tektronix, Inc., Beaverton, Oreg., are examples of such signal generators.
FIG. 1 is an exemplary block diagram of a signal generator. A CPU (Central Processing Unit) 10 controls the signal generator system according to program stored in a hard disk drive (HDD) 14. The HDD 14 may also be used for storing a large amount of data, such as waveform generation software, digital waveform data and the like. A memory 12, such as RAM memory, is used for a work area for the CPU 10 to read programs from the storage device. A user can set up the signal generator via an operation panel 24 that includes keys, knobs, and the like. A display 22 provides visual information relating to signal patterns and user settings. An external display output circuit 20 provides a video output which may be connected to an external display 32 for providing a larger display area in addition to the built-in display 22 of the signal generator. A signal generation circuit 16 generates signal patterns based on user defined parameters. In this example, it has two channel outputs and inputs for trigger and event signals. Receipt of these signals enables conditional actions. An input/output port 28 is used for connecting an external keyboard 29, a pointing device 30, such as a mouse, and the like to the signal generator. The external keyboard 29 and/or pointing device 30 may be included as parts of the operation means of the signal generator. These blocks are coupled together via a bus 18. A LAN (Local Area Network) interface may be connected to the bus 18 to couple the signal generator to an external PC 34. The external PC 34 allows a user to remotely control the signal generator as desired.
FIG. 2 is a block diagram of a conventional signal generation circuit. For simplicity, a circuit having only one channel is shown but the operation of a two-channel circuit is similar. A reference clock generator 52 generates a reference clock which is coupled to a digital-to-analog converter (DAC) 48. The reference clock sets the timing of sampling points of an analog electric signal generated by the DAC 48. The reference clock may be referred to as a sampling clock in case of a signal generator. A divider 50 divides the reference clock by dividing ratio n (n is a natural number) to generate a divided clock that is synchronous with the reference clock but has a clock frequency of 1/n. The divided clock sets the timing for reading waveform data from a waveform memory 44.
The waveform memory 44 may be relatively fast operating memory such as SRAM (Static Random Access Memory) and stores waveform data as parallel data. In this example, let the bit number of the parallel data be m (m is a natural number). A sequence memory 40 stores sequence (output order) information for reading the waveform data from the waveform memory 44. A sequencer 42 derives addresses from the sequence information and provides the addresses to the waveform memory 44. The waveform memory 44 provides the waveform data as m-bit parallel data to a parallel-to-serial converter (P/S) 46.
The parallel-to-serial converter 46 receives the waveform data according to the divided clock and converts the m-bit parallel data to a lower bit number (K bit in this example; K is a natural number and less than m) parallel data and provides the K-bit parallel data to the DAC 48 according to the reference clock. A relationship exists between the m-bit parallel data and the K-bit parallel data in the form of m=K×n. These processes reduce the bit number but produces faster data according to the reference clock that is n times faster than the waveform data being read out from the waveform memory 44 according to the divided clock. At present, read-out speed of the memory is not high enough to produce a desired high frequency analog signal from the DAC 48. However, sufficient data acceleration is achieved by the parallel-to-serial converter 46 to generate a high frequency analog signal. The DAC 48 converts the K-bit parallel data to produce an analog electric signal. The output of the DAC is passed through a low pass filer (not shown) to produce a smooth analog signal as is known. One set of the parallel data may also be called one word because it corresponds to one sampling point of the output from the signal generator.
In the data acceleration described above, the data length after the data acceleration of the parallel to serial conversion through the P/S converter 46 is limited to an integer multiple of m since one set of the waveform data has m bits of data. That is, the parallel data that the DAC 48 receives can not have an arbitrary word length. For example, if m is 64 and K is 10, then 10 sets of 64 bit parallel data are read out. The number of the data bits is 640 which can be converted to 64 sets (words) of 10 bit parallel data. However, if 9 sets of 64 bit parallel data are read out, the total number of the data bits is 576 which can be converted to 57 sets (words) of 10 bit parallel data with 6 data bits left over that can not constitute one set of 10 bit parallel data.
U.S. Patent Application Publication 2006/0155898 discloses one solution on the above problem. A data memory provides 5 bit parallel data of which 4 bit or 5 bit data are effective, and a bit width identifier signal that indicates effective bit width of the parallel data to a FIFO (First In First Out) memory. The FIFO memory provides 4 bit parallel data having only the effective data using the bit width identifier signal, and then the 4 bit parallel data is converted to serial data. The combination of the 4 bit and 5 bit effective parallel data realizes a series of the effective data having an arbitrary length.
A signal generator is increasingly required to provide a signal of higher frequency for characteristic testing of a fast serial interface. At the same time, the signal generator should provide large amount of waveform data at low cost. Then, use of a lower cost memory such as DDR3 SDRAM as the waveform memory in place of an expensive SRAM may be considered for storing a large amount of data at low cost. Further, the use of FPGA (Field Programmable Gate Array) in place of dedicated ASIC (Application Specific Integrated circuits) may be preferable to achieving low cost even though a FPGA does not work as fast a an ASIC.